st7/
;procesor: ST7FLITE39F
;*********************************************************
	.NOLIST
	#INCLUDE "ST7FLITE39.inc"
	.LIST
;*********************************************************
;-------------- definice --------------------------
PADDR_1	equ	%10011111	; pro ladeni
											
PBDDR_1 equ %11011111
jednicka equ %11111110
;-------------- blok pameti RAM --------------------------
				BYTES
				segment 'ram0'
pr_cekej1  DS.B				 
pr_cekej2  DS.B
test  		 DS.B
;-------------- vlastni program --------------------------
				WORDS
        segment 'rom'
.main 	LD A,#PADDR_1
				LD PADDR,A			

.zacatek
				LD X,#jednicka
				SCF
				LD A,#5
				LD test,A
.znova  
				LD PADR,X
				RLC X
				CALL wait				
				DEC test
				JRNE znova
				LD A,#5
				LD test,A
.znovazpet
				RRC X
				LD PADR,X
				CALL wait				
				DEC test
				JRNE znovazpet
				JP zacatek


												; 2 * 0.1 s tj cca 0.1 s
;-------------- podprogram cekani ------------------------
.wait  	
				LD	A,#200	
				LD pr_cekej2,A	
wait2		LD	A,#250		
				LD pr_cekej1,A	
wait1		DEC pr_cekej1		
				JRNE wait1			
				DEC pr_cekej2		
				JRNE wait2			
				RET							

;------------- obsluha preruseni ---------------------------
.dummy   iret   	

;------------- vektory preruseni ---------------------------
				segment 'vectit'
                DC.W    dummy 	;13 FFE0-FFE1h AT TIMER
                DC.W    dummy   ;12 FFE2-FFE3h SPI
                DC.W    dummy   ;11 FFE4-FFE5h LITE TIMER  
								DC.W    dummy   ;10 FFE6-FFE7h LITE TIMER  
								DC.W    dummy	  ; 9 FFE8-FFE9h AT TIMER 
								DC.W    dummy   ; 8 FFEA-FFEBh AT TIMER  
								DC.W    dummy   ; 7 FFEC-FFEDh SI   
                DC.W    dummy   ; 6 FFEE-FFEFh LINSCI
                DC.W    dummy   ; 5 FFF0-FFF1h LITE TIMER  
								DC.W    dummy   ; 4 FFF2-FFF3h EI3
								DC.W    dummy   ; 3 FFF4-FFF5h EI2
								DC.W    dummy   ; 2 FFF6-FFF7h EI1   
								DC.W    dummy   ; 1 FFF8-FFF9h EI0
                DC.W    dummy   ; 0 FFFA-FFFBh AWU
								DC.W    dummy   ; T FFFC-FFFDh TRAP
.reset          DC.W    main    ; R FFFE-FFFFh RESET

;-------------- konec zdrojoveho textu direktiva END -------
		END